1. Technical Field of the Invention
The present invention relates to a high speed digital phase locked loop (PLL) circuit which is easily manufactured in the form of an integrated circuit (IC).
2. Description of the Prior Art
Recently, various PLL circuits have been developed, because a clock recovery circuit using the PLL circuit is important for providing a small sized apparatus for data transmission.
For example, a PLL circuit of which phase comparator comprises delay flip-flops (DFF) is disclosed in xe2x80x9cA Monolithic 2,3-Gb/s 100 mV Clock and Data Recovery Circuit in Silicon Bipolar Technologyxe2x80x9d IEEE Journal of Solidxe2x80x94State Circuit. VOL.28, NO.12, pp. 1310-1313, December 1993.
A conventional PLL circuit is shown in FIG. 7. The PLL circuit as shown in FIG. 7 comprises phase comparator 50, filter 51, voltage controlled oscillator (VCO) 52, and determination means 53. Further, phase comparator 50 comprises first DFF 54 and second DFF 55.
The clock signal from VCO 52 is sampled by the data signal inputted into first DFF 54 and second DFF 55. Concretely, first DFF 54 samples the clock signal at the rise up of the data signal, while second DFF 55 samples the clock signal at the fall down of the data signal. Therefore, the clock signal is sampled by the two DFFs in turns.
For example, When the data signal is such that xe2x80x9c1xe2x80x9d follows xe2x80x9c0xe2x80x9d, the phase of the clock signal from VCO 52 is delayed. In this case, the phase of the clock signal is advanced. In other words, the frequency of the clock signal is raised. On the other hand, when the data signal is such that xe2x80x9c0xe2x80x9d follows xe2x80x9c1xe2x80x9d, the phase of the clock signal from VCO 52 is advanced. In this case, the phase of the clock signal is delayed. In other words, the frequency of the clock signal is lowered. Thus, the data signal is synchronized with the clock signal, because the transition point of the data signal coincides with the fall down point of the clock signal.
By using thus obtained clock signal, the data signal is outputted from determination means 53. The digital circuit by the Si bipolar transistors for determination means 53 can attain higher speed than analog phase comparator.
However, the Si bipolar transistors consume much electric power. The power consumption of CMOS is low, although the speed of CMOS is low in general.
Therefore, an object of the present invention is to provide a high speed PLL circuit by CMOS for non-return to zero (NRZ) signal.
In the PLL circuit of the present invention, a phase of data signal is locked with a first clock of which frequency is the half of the data signal. Further, a second clock of which phase is shifted by xcfx80/2 compared with the first clock is used for determining phase delay or phase advance of the data signal compared with the first clock.
The PLL circuit of the present invention comprises: a voltage controlled oscillator for outputting the first clock and the second clock; a phase comparator for inputting the data signal, the first clock, and the second clock, and for outputting a first data sampled at fall down of the first clock, a second data sampled at rise up of the first clock, a first indication signal indicating the phase delay, and a second indication signal indicating the phase advance; and a filter for inputting the first indication signal and the second indication signal, and for outputting a control voltage which controls the phase of the first clock outputted from the voltage controlled oscillator.
The phase comparator comprises a data sampling circuit and a phase determination circuit.
The data sampling circuit comprises a first determination means for outputting the first data, a second determination means for outputting the second data, a first delay flip-flop (DFF), and a second DFF, wherein: the data signal and an inverted signal of sad first clock are inputted into the first determination means; the data signal and the first clock are inputted into the second determination means; the data signal and the second clock are inputted into the first DFF; and the data signal and an inverted signal of the second clock are inputted into the second DFF.
The phase determination circuit comprises a first AND circuit, a second AND circuit, a third AND circuit, a fourth AND circuit, a first OR circuit for outputting the first indication signal, and a second OR circuit for outputting the second indication signal, wherein: the inverted logic output from the first determination means, the positive logic output from the second determination means, and the positive logic output from aid first DFF are inputted into the first AND circuit; the inverted logic output from the first determination means, the positive logic output from the second determination means, and the inverted logic output from the first DFF are inputted into the second AND circuit; the positive logic output from the first determination means, the inverted logic output from the second determination means, and the positive logic output from the second DFF are inputted into the third AND circuit; the positive logic output from the first determination means, the inverted logic output from the second determination means, and the inverted logic output from the second DFF are inputted into the fourth AND circuit; the output from the first AND circuit and the output from the third AND circuit is inputted into the first OR circuit; and the output from the second AND circuit and the output from the fourth AND circuit is inputted into the first OR circuit.
Further, the phase determination circuit may comprise a third DFF for sampling the first indication signal and a fourth DFF for sampling the second indication signal, wherein: the output from the first OR circuit and the second clock are inputted into the third DFF; and the output from the second OR circuit and the second clock are inputted into the fourth DFF.
Further, the first and second determination means may be delay flip-flops.
Further, the first and second determination means may comprise, respectively, a first latch circuit for inputting the data signal, a second latch circuit for inputting the output from the first latch circuit, and a third latch for inputting the output from the second latch circuit.
In the above-mentioned first determination means, the first clock is inputted into the clock terminals of the first and third latch circuits; the inverted signal of the first clock is inputted into the clock terminal of the second latch; the output from the second latch circuit is the positive logic output, and the output from the third latch circuit is the inverted logic output.
On the other hand, in the above-mentioned second determination means, the inverted first clock is inputted into the clock terminals of the first and third latch circuits; the inverted signal of the inverted first clock is inputted into the clock terminal of the second latch; the output from the second latch circuit is the positive logic output, and the output from the third latch circuit is the inverted logic output.
The positive logic output from the third latch circuit in the first determination means is outputted from the data sampling circuit, while the positive logic output from the third latch circuit in the second determination means is outputted as the second data from the data sampling circuit.
In the PLL circuit of the present invention, the first clock signal CLK0 of which frequency is the half of the bit rate of the data signal is synchronized with the data signal. Further, the data signal is sampled at the fall down and rise up of the clock. The first clock CLK0 for data separation is not sufficient for determining whether the phase of CLK0 is delayed or advanced. Therefore, the second clock CLK90 of which phase is shifted by xcfx80/2 compared with CLK0 is employed.
The inputted data signal is sampled at the four points; both edges of CLK0 and CLK90, and the phases are compared, by using three edges; two edges of CLK0 and one edge of CLK90 which is in between the two edges of CLK0. Here, sampling points are provisionally assumed to be ta, tb, tc from past toward present in time order, and sa, sb,sc are the data signal sampled at the times ta, tb,tc. Therefore, sa and sc are sampled by CLK0, while sb is sampled by CLK90.
The phase of CLK0 is determined to be advanced, when sa is the same as sb, and is different from sc. In this case, the DOWN signal is generated. On the other hand, the phase of CLK0 is determined to be delayed, when sb is the same as sc.
A voltage is generated by the filter on the basis of the UP or DOWN signal is fed back into VCO for generating CLK0 and CLK90 of which frequency is the half of the bit rate of the data signal. Therefore, the PLL circuit of the present invention can deal with high bit rate data. The PLL circuit of the present invention can be small in size, because the determination means in the data sampling circuit can be used also for separating inputted data signal.
Concretely, the CMOS PLL circuit of the present invention operated at high speed for the input signal up to 2.4 Gb/s.
Particularly, according to the second embodiment, the convergent time of the PLL circuit was shortened, because the gain of the phase comparator is higher than that of the phase comparator in the first embodiment.
Further, particularly according to the third embodiment, the operation speed became 1.5 times of that in the second embodiment.